Publications

 

Refereed Journal Articles – in-press

  1. None at present

Refereed Journal Articles – published

  1. Ramin Rajaei+, Mohammad Mehdi Sharifi@, Arman Kazemi@, Michael Niemier, and X. Sharon Hu, “Compact Single-Phase-Search Multi-State Content Addressable Memory Design using 1 FeFET/Cell,” IEEE Transactions on Electron Devices; DOI: 10.1109/TED.2020.3039477; Volume 68(1), p. 109-117, 2021.
  2. Dayane Reis@, Jonathan Takeshita, Taeho Jung, Michael Niemier and X. Sharon Hu, “Accelerating Fully Homomorphic Encryption with Computing-in-Memory,” November, 28(11), p. 2300-2313, IEEE Transactions on VLSI, 2020. 10.1109/TVLSI.2020.3017595.
  3. Mohsen Imani, Xunzhao Yin@, John Messerly, Saransh Gupta, Michael Niemier, X. Sharon Hu, and Tajana Rosing, “SearcHD: A Memory-Centric Hyperdimensional Computing with Stochastic Training,” IEEE Transactions on CAD, 10.1109/TCAD.2019.2952544, October 2020 39(10), p. 2422-2433.
  4. X. Yin, C. Li, Q. Huang, L. Zhang, M. Niemier, X.S. Hu, C. Zhou, K. Ni, "FeCAM:  A Universal Compact Digital and Analog Content Addressable Memory Using Ferroelectric," IEEE. T. on Electron Devices, 67(7), p. 2785-2792, 2020.
  5. Xiaoming Chen+, Suman Datta, Xiaobo Sharon Hu, Matthew Jerry@, Ann Franchesca Laguna@, Kai Ni+, Michael Niemier, Dayane Reis@, Xiaoyu Sun, Panni Wang, Xunzhao Yin@, and Shimeng Yu, “The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures,” IEEE Design and Test (invited), (37)1, 2020.
  6. Chenyun Pan, Qiuwen Lou@, Michael Niemier, X. Sharon Hu, and Azad Naeemi, “Energy-Efficient Convolutional Neural Netowrk based on Cellular Neural Network Using Beyond CMOS Technologies,” IEEE JxCDC, 5(2), p. 85-93, 2019.
  7. Kai Ni+, Xunzhao Yin@, Ann Franchesa Laguna@, Siddharth Joshi, Stefan Dunkel, Martin Trentzsch, Johannes Mueller, Sven Beyer, William Taylor, Michael T. Niemier, Xiaobo Sharon Hu, and Suman Datta, “Ferroelectric Ternary Content Addressable Memory for One-Shot Learning,” Nature Electronics, 2(11), p. 521-529, 2019
  8. Dayane Reis@, Michael Niemier, X. Sharon Hu, “A Computing-in-Memory Engine for Searching on Homomorphically Encrypted Data,” in IEEE JxCDC, 2019, DOI: 10.1109/JXCDC.2019.2931889
  9. Andrew W. Stephan, Qiuwen Lou@, Michael Niemier, X. Sharon Hu, and Steven J. Koester, “Nonvolatile Spintronic Memory Cells for Neural Networks,” in IEEE JxCDC, 5(2), p. 67-78, 2019.
  10. Dayane Reis@, Kai Ni+, Wriddhi Chakraborty, Xunzhao Yin@, Martin Trentzsch, Stefan Dunkel, Thomas Melde, John Mueller, Sven Beyer, Suman Datta, Michael Niemier and X. Sharon Hu, “Design and analysis of an ultra-dense, low-leakage and fast FeFET-based random access memory array,” accepted in IEEE JxCDC, 2019, DOI: 10.1109/JXCDC.2019.2930284
  11. An Chen, Supriyo Datta, X. Sharon Hu, Michael Niemier, Tajana Simunic Rosing, J. Joshua Yang, “A Survey of Architecture Advances Enabled by Emerging Beyond-CMOS Technologies,” IEEE Design and Test, 36(3), p. 46-68, 2019 (invited).
  12. Qiuwen Lou@, Chenyun Pan, John McGuinness*, Andras Horvath, Azad Naeemi, Michael Niemier, and X. Sharon Hu, “A Mixed Signal Architecture for Convolutional Neural Networks,” ACM Journal on Emerging Technologies in Computing Systems, 15(2) p.19, 2019.
  13. Xunzhao Yin@, Kai Ni+, Dayane Reis@, Suman Datta, Michael Niemier, and Xiaobo Sharon Hu, “An Ultra-dense 2FeFET TCAM Design based on a Multi-Domain FeFET Model,” IEEE Transactions on Circuits and Systems II, 66(9), p. 1577-1581, 2019.
  14. Xunzhao Yin@, Michael Niemier, and X. Sharon Hu, “Exploiting Ferroelectric FETs for Low-Power, Non-Volatile Logic-in-Memory Circuits,” IEEE Transactions on VLSI, 27(1), p. 159-172.
  15. Xiaoming Chen+, Michael Niemier, Yinhe Han, and Xiaobo Sharon Hu, “Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs,” IEEE Transactions on Circuits and Systems I: Regular Papers, p. 1780-1893, 2018.
  16. Xiaobo Sharon Hu and Michael Niemier, “Cross-Layer Efforts for Energy Efficient Computing – Towards Peta Operations Per Second Per Watt,” Frontiers of Information Technology and Electronic Engineering, 19(10), p. 129-1223, 2018.
  17. Matthew Jerry@, Sourav Dutta+, Arman Kazemi@, Kai Ni+, Jianchi Zhang, Pai-Yu Chen, Pankaj Sharma, Shimeng Yu, Sharron Hu, Michael Niemier, and Suman Datta, “A Ferroelectric Field Effect Transistor-based Non-Volatile Analog Synpatic Memory,” Journal of Physics D, 117172.R1 2018.
  18. X. Xu, Y. Ding, S.X. Hu, M. Niemier, J. Cong, Y. Hu, and Y. Shi, “Scaling of Deep Neural Networks for Edge Inference: A Race Between Data Scientists and Hardware Architects,” Nature Electronics, 1(4), 216, 2018.
  19. Robert Perricone@, X. Sharon Hu, Joseph Nahas, and Michael Niemier, “Can Beyond-CMOS Devices Illuminate Dark Silicon?” Communications of the ACM, 61(9), p. 60-69, 2018.
  20. Jorge Fernández-Berni, Michael Niemier, X. Sharon Hu, Wenjun Li@, Patrick Fay, and Ricardo Carmona Galán, “TFET-based Well Capacity Adjustment in Active Pixel Sensor for Enhanced High Dynamic Range” Electronics Letters, 53(9), p. 622-624, 2017.
  21. Yu Bi, Kaveh Shamsi, Jiann-Shiun Yuan, Yier Jin, Michael Niemier, and X. Sharon Hu, “Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs,” in IEEE Transactions on Emerging Topics in Computing, 5(3) p. 340-52, 2017.
  22. Robert Perricone@, Yang Liu@, Aaron Dingler@, X. Sharon Hu, and Michael Niemier, “Design of Stochastic Computing Circuits using Nanomagnetic Logic,” in IEEE Transactions on Nanotechnology, 15(2), p. 179-187, 2016.
  23. Y. Bi, K. Shamsi, P.-E. Gaillardon, G. de Micheli, X. Yin, X. Hu, M. Niemier, J.-S. Yuan, and Y. Jin, “Emerging technology based design primitives for hardware security,” ACM Journal of Emerging Technologies in Computing Systems, 13(1), 3:1-3:19, 2016.
  24. Wolfgang Porod and Michael Niemier, “Building Ultra-Energy Efficient Computers Out of Tiny Bar Magnets,” IEEE Spectrum, 52, p. 44-60, 2015 (invited).
  25. Faisal A. Shah@, György Csaba+, Michael T. Niemier, Xiaobo S. Hu, Wolfgang Porod, and Gary Bernstein, “Error Analysis for Ultra Dense Nanomagnet Logic Circuits,” Journal of Applied Physics, 117(17), 274591JAP, 2015.
  26. B. Sedighi+, X. Sharon Hu, Joseph J. Nahas, and Michael Niemier, “Nontraditional Computation using Beyond-CMOS Tunneling Devices,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, p. 438-449, December 2014.
  27. Katie Butler@, Gary Bernstein, György Csaba+, X. Sharon Hu, Michael Niemier, and Wolfgang Porod, “Contiguous Clock Lines for Pipelined Nanomagnet Logic,” Journal of Computational Electronics, 13(3), p. 763-768, 2014.
  28. Ádam Papp@, Michael T. Niemier, Árpád Csurgay, Markus Becherer, Stephan Breitkreutz, Josef Kiermaier, Irina Eichwald, X. Sharon Hu, Xueming Ju, Wolfgang Porod, and György Csaba+, “Threshold Gate-Based Circuits from Nanomagnet Logic,” IEEE Transactions on Nanotechnology, 13(5), p. 990-996, 2014.
  29. Behnam Sedighi+, Xiaobo Sharon Hu, Huichu Liu&, Joseph J. Nahas, and Michael Niemier, “Analog Circuit Design Using Tunnel-FETs,” in IEEE Journal on Circuits and Systems I, 62(1), p. 39-48, 2014.
  30. M. A. Siddiq@, K. Butler@, H. Dey@, F. Shah@, P. Li@, E. Varga@, A. O. Orlov, G. Csaba+, M. T. Niemier, W. Porod, G. H. Bernstein, “Nanomagnet Logic Gate with Programmable-Electrical Input,” IEEE Transactions. on Magnetics, 50(11), 3401604, 2014.
  31. Michael Niemier, “Clocking with no Field,” Nautre Nanotechnology, Vol. 9, p. 14-15, January, 2014.
  32. Mohammad Abu Jafar Siddiq@, M.T. Niemier, G.H. Bernstein, W. Porod, X.S. Hu, “A Nanomagnet Logic Field Coupled Input,” IEEE Transactions on Nanotechnology, 12(5) p. 734-742, 2013.
  33. Edit Varga@, M.T. Niemier, G. Csaba+, G.H. Bernstein, and W. Porod, “Experimental Realization of a Nanomagnet Full Adder Using Slanted-Edge Magnets,” IEEE Transactions on Magnetics, 49(7), 4452-4455, 2013.
  34. M.A. Siddiq@, M. Niemier, G. Csaba+, X.S. Hu, W. Porod, and G.H. Bernstein, “Demonstration of Field Coupled Input Scheme on Line of Nanomagnets,” IEEE Transactions on Magnetics, 49(7), p. 4460-4463, 2013.
  35. Himadri Dey@, Gyorgy Csaba+, X. Sharon Hu, Michael Niemier, Gary Bernstein, and Wolfgang Porod, “Switching Behavior of Sharply Pointed Nanomagnets for Logic Applications,” IEEE Transactions on Magnetics, 49(7), p. 3549-3552, 2013.
  36. Xueming Ju, Michael Niemier, Markus Becherer, Wolfgang Porod, Paolo Lugli, and György Csaba+, “Systolic Pattern Matching Hardware with Out-of-Plane Nanomagnet Logic Devices,” IEEE Transactions on Nanotechnology, 12(3), p. 399-407, 2013.
  37. Peng Li@, Gyorgy Csaba+, Michael Niemier, X. Sharon Hu, Joseph Nahas, Wolfgang Porod, and Gary H. Bernstein, “Power Reduction in Nanomagnet Logic using High Permeability Dielectrics,” Journal of Applied Physics, 113(17), 17B906-17B906-3, 2013.
  38. Shiliang Liu&, X. Sharon Hu, Michael T. Niemier, Joseph J. Nahas, Gary H. Bernstein, and Wolfgang Porod, “Exploring the Design of the Magnetic-Electrical Interface for Nanomagnet Logic,” IEEE Transactions on Nanotechnology, 12(2), p. 203-214, 2013.
  39. Peng Li@, Vijay K. Sankar+, Gyorgy Csaba+, X. Sharon Hu, Michael Niemier, Wolfgang Porod, Gary H. Bernstein, “Magnetic Properties of Enhanced Permeability Dielectrics for NML Circuits,” IEEE Transactions on Magnetics, 48(11), p. 3292-3295, 2012.
  40. Peng Li@, Gyorgy Csaba+, Vijay K. Sankar+, Xueming Ju, Edit Varga@, Paolo Lugli, X. Sharon Hu, Michael Niemier, Wolfgang Porod, and Gary Bernstein, “Direct Measurement of Magnetic Coupling between Nanomagnets for NML Applications,” IEEE Transactions on Magnetics,48(11), p. 4402-4405, 2012.
  41. M. Tanvir Alam@, Steven Kurtz@, M. Jafar Siddiq@, Michael T. Niemier, Gary H. Bernstein, Xiaobo Sharon Hu, and Wolfgang Porod, “On-chip Clocking of Nanomagnet Logic Lines and Gates,” in IEEE Transactions on Nanotechnology, 11(2), p. 273-286, 2012.
  42. M. Niemier, E. Varga@, G. H. Bernstein, W. Porod, M. T. Alam@, A. Dingler@, A. Orlov, and X. Sharon Hu, “Shape Engineering for non-majority Boolean gate designs with nanomagnet logic,” in IEEE Transactions on Nanotechnology, 11(2), p. 220-230, 2012.
  43. Peng Li@, Gyorgy Csaba+, Vijay K. Sankar+, Xueming Ju, Paolo Lugli, X. Sharon Hu, Michael Niemier, Wolfgang Porod, Gary H. Bernstein, “Switching Behavior of Lithographically Fabricated Nanomagnets for Logic Applications,” Journal of Applied Physics, 111, 07B911, April 2012.
  44. M. Crocker&, M.T. Niemier, and X.S. Hu “A Reconfigurable PLA Architecture for Nanomagnet Logic,” ACM Journal of Emerging Technology and Computing Systems, ACM Journal on Emerging Technologies in Computing, Vol. 8, No. 1, p. 1-25, February, 2012.
  45. M.T. Niemier, G.H. Bernstein, A. Dingler@, X.S. Hu, S. Kurtz@, S. Liu&, J. Nahas, W. Porod, M. Siddiq@, and E. Varga@, “Nanomagnet Logic: Progress Toward System-Level Integration,” in Journal of Physics: Condensed Matter, 23, 493202, 2011.
  46. S. Liu&, X. Sharon Hu, Joseph J. Nahas, Michael Niemier, Wolfgang Porod, and Gary H. Bernstein, “Magnetic-Electrical Interface for Nanomagnet Logic,” in IEEE Transactions on Nanotechnology, 10(4), p. 757-763, 2011.
  47. Aaron Dingler@, Michael T. Niemier, Xiaobo Sharon Hu, and Evan Lent*, “Performance and Energy Impact on Locally Controlled NML Circuits,” in ACM Journal on Emerging Technologies in Computing, 7(1), p. 1-24, 2011.
  48. Steven Kurtz@, Edit Varga@, Michael Niemier, Wolfgang Porod, Gary H. Bernstein, and X. Sharon Hu, “Two Input, Non-Majority Magnetic Logic Gates: Experimental Demonstration and Future Prospects,” in Journal of Physics: Condensed Matter, 23(5), p. 053202, 2011.
  49. Mohmmad Tanvir Alam@, Mohammad Jafar Siddiq@, Gary H. Bernstein, Michael Niemier, Wolfgang Porod, and X. Sharon Hu, “On-chip Clocking for Nanomagnet Logic Devices,” IEEE Transactions on Nanotechnology, p. 348-351, Volume 9(3), 2010.
  50. Edit Varga@, Alexei Orlov, Michael T. Niemier, X. Sharon Hu, Gary H. Bernstein, Wolfgang Porod, “Experimental Demonstration of Fanout for Nanomagnet Logic,” in IEEE Transactions on Nanotechnology, 9(6), p. 668-670, 2010.
  51. M. Crocker&, X.S. Hu, and M.T. Niemier, “Defects and Faults in QCA-Based PLAs,” ACM Journal of Emerging Technology and Computing Systems, Vol. 5, No. 2, p. 1-27, 2009.
  52. M. Crocker&, M. Niemier, X. Sharon Hu, and M. Lieberman, “Molecular QCA design with chemically reasonable constraints,” ACM Journal of Emerging Technology and Computing Systems, Vol. 4, No. 2, p. 1-21, 2008.
  53. A. Chaudhary, D. Z. Chen, X.S. Hu, M. T. Niemier, R. Ravichandran@, and K. Whitton, “Easing Fabricatable Interconnect in Molecular QCA Circuits,” in IEEE Transactions on CAD (TCAD), p. 1978-1991, Vol. 26(11), November 2007.
  54. S.K. Lim, R. Ravichandran@, and M.T. Niemier, “Partitioning and Placement for Buildable QCA Circuits,” in ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 1, No. 1, p.50-72, 2005.
  55. R. Ravichandran@, S.K. Lim, and M.T. Niemier, “Automatic Cell Placement for Quantum-dot Cellular Automata,” in Integration: The VLSI Journal, Vol. 38, No. 3, p.541-548, 2005.
  56. M.T. Niemier and P.M. Kogge, “Problems in Designing with QCAs: Layout = Timing,” in International Journal of Circuit Theory and Applications, 29: 49-62, 2001.

Refereed Conference and Workshop Papers – in-press

  1. Hussam Amrouch, Xiaobo Sharon Hu, Mohsen Imani, Ann Franchesca Laguna@, Michael Niemier, Simon Thomann, Xunzhao Yin, Cheng Zhuo, “Cross-Layer Design for Computing-in-Memory: From Devices,Circuits, to Architectures and Applications,” to appear / invited at ASP-DAC, 2021.
  2. Dayane Reis@, Michael Niemier, and X. Sharon Hu, “Attention-in-Memory for Few Shot Learning with Configurable Ferroelectric FET Arrays,” to appear at ASP-DAC, 2021. 
  3. Arman Kazemi@, Mohammad Mehdi Sharifi@, Ann Franchesca Laguna@, Ramin Rajaei+, Michael T. Niemier, and X. Sharon Hu, “FeCAM: A Universal Compact Digital and Analog Content Addressable Memory Using Ferroelectric,” to appear at Design Automation and Test in Europe, 2021. 
  4. Ann Franchesca Laguna@, Arman Kazemi@, Michael Niemier and X. Sharon Hu, “In-Memory Computing based Accelerator for Transformer Networks for Long Sequences,” to appear at Design Automation and Test in Europe, 2021. 
  5. Dayane Reis@, Ann Franchesca Laguna@, Michael Niemier, and Xiaobo Sharon Hu, “Exploiting FeFETs via Cross-Layer Design from In-memory Computing Circuits to Meta-Learning Applications,” to appear / invited at Design Automation and Test in Europe, 2021. 
  6. Ann Franchesca B. Laguna@, Hasindu Gamaarachchi, Xunzhao Yin, Michael T. Niemier, Sri Parameswaran, X.Sharon Hu, “Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping,” to appear in International Conference on Computer Aided Design (ICCAD).

 

Refereed Conference and Workshop Papers – published

  1. Jonathan Takeshita, Dayane Reis@, Ting Gong, Michael Niemier, X. Sharon Hu, and Taeho Jung, “Algorithmic Acceleration of B/FV-likeSomewhat Homomorphic Encryption for Compute-RAM,” International Conference on Selected Areas in Cryptography. Springer, Cham, 2020. 
  2. Ann Franchesca B. Laguna@, Hasindu Gamaarachchi, Xunzhao Yin, Michael T. Niemier, Sri Parameswaran, X.Sharon Hu, “Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping,” in International Conference on Computer Aided Design (ICCAD), 2020. 
  3. Arman Kazemi@, Cristobal Alessandri, Alan C. Seabaugh, X. Sharon Hu, Michael Niemier and Siddharth Joshi, “A Device Non-ideality Resilient Approach for Mapping Neural Networks to Resistive Crossbar Arrays,” at Design, Automation Conference, 2020.
  4. Arman Kazemi@, Ramin Rajaei+, Kai Ni, Suman Datta, Michael Niemier, X. Sharon Hu, “A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference,” at IEEE International Symposium on Circuits and Systems, 2020.
  5. Ramin Rajaei+, Yen-Kai Lin, Sayeef Salahuddin, Michael Niemier, X. Sharon Hu, “Dynamic Memory and Sequential Logic Design using Negative Capacitance FinFETs,” at IEEE International Symposium on Circuits and Systems, p. 1-5 2020.
  6. D Ma, X Yin, M Niemier, XS Hu, X Jiao, “AxR-NN: Approximate Computation Reuse for Energy- Efficient Convolutional Neural Networks,” Proceedings of the Great Lakes Symposium on VLSI, 363-368, 2020. 
  7. D Reis, D Gao, S Angizi, X Yin, D Fan, M Niemier, C Zhuo, XS Hu, “Modeling and benchmarking computing-in-memory for design space exploration,” Proceedings of the Great Lakes Symposium on VLSI, 39-44, 2020. 
  8. Ramin Rajaei+, Yen-Kai Lin, Sayeef Salahuddin, Michael Niemier, Xiaobo Sharon Hu, “GC-eDRAM Design using Hybrid FinFET/NC-FinFET,” IEEE International Symposium on Low Power Electronics and Design, p. 199-204, 2020. 
  9. Qiuwen Lou@, X. Sharon Hu, Michael Niemier, Siddharth Joshi, “Embedding Error Correction into Crossbars for Reliable Matrix Vector Multiplication using Emerging Devices,” in IEEE International Symposium on Low Power Electronics and Design, p. 139-144, 2020. 
  10. David Brooks, Martin M. Frank, Tayfun Gokmen, Udit Gupta, X. Sharon Hu, Shubham Jain, Ann Franchesca Laguna, Michael Niemier, Anand Raghunathan, Ashish Ranjan, Dayane Reis, Jacob R. Stevens, Carole-Jean Wu, Xunzhao Yin, “Emerging Neural Workloads and Their Impact on Hardware,” Design, Automation, and Test in Europe (DATE), (invited), 10.23919/DATE48585.2020.9116435, p. 1462-1471, 2020. 
  11. Dayane Reis@, Ann Franchesca Laguna@, Michael Niemier, and X. Sharon Hu, “A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning Applications,” Design, Automation, and Test in Europe (DATE), 10.23919/DATE48585.2020.9116292, p. 127-132, 2020. 
  12. Mohammad Mehdi Sharifi@, Ramin Rajaei+, Patsy Cadareanu, Pierre-Emmanuel Gaillardon, Yier Jin, Michael Niemier and X. Sharon Hu, “A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks,” Design, Automation, and Test in Europe (DATE), 10.23919/DATE48585.2020.9116554, p. 1253-1258, 2020.
  13. Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis@, Di Gao, Xunzhao Yin@, Michael Niemier, Cheng Zhou, X. Sharon Hu, “The Impact of Emerging Technologies on Architectures and System-level Management,” (invited) at International Conference on Computer Aided Design (ICCAD), 2019.
  14. Indranil Palit@, Qiuwen Lou@, Robert Perricone@, Michael Niemier, and X. Sharon Hu, “A Uniform Modeling Methodology for Benchmarking DNN Accelerators,” under review at International Conference on Computer Aided Design (ICCAD), 2019.
  15. Xunzhao Yin@, Dayane Reis@, Xiaobo Sharon Hu and Michael Niemier, “Ferroelectric FET based TCAM Designs for Energy Efficient Computing,” at IEEE Computer Society’s Symposium on VLSI (ISVLSI), (invited), p. 437-442, 2019.
  16. Ann Franchesca Laguna@, Xunzhao Yin@, Dayane Reis@, Michael Niemier, X. Sharon Hu, “Ferroelectric FET-based In-Memory Computing for Few-Shot Learning,” at Great Lakes Symposium on VLSI (GLSVLSI), p. 373-378, 2019 (invited).
  17. Matthew Jerry@, Sourav Dutta+, Kai Ni+, Jianchi Zhang, Pankaj Sharma, Suman Datta, Arman Kazemi@, X. Sharon Hu, Michael Niemier, Pai-Yu Chen, Shimeng Yu, “Ferroelectric FET-based Non-Volatile Analog Synaptic Weight Cell,” at GoMacTech, 2019.
  18. Ann Franchesca Laguna@, Michael Niemier, and X. Sharon Hu, “Design of Hardware Friendly Memory Enhanced Neural Networks,” at Design Automation and Test in Europe (DATE), 2019.
  19. Robert Perricone@, Zhaoxin Liang, Meghna Mankalale, Michael Niemier, Sachin S. Sapatnekar, Jian-Ping Wang and X, Sharon Hu, “An Energy Efficient Non-Volatile Flip-Flop based on CoMET Technology,” at Design Automation and Test in Europe (DATE), 2019.
  20. Xunzhao Yin@, Kai Ni+, Dayane Reis@, Suman Datta, Michael T. Niemier, and X. Sharon Hu, “Design and Benchmarking of Ferroelectric FET TCAMs based on a multi-domain model,” at TECHCON, Austin, TX, 2018.
  21. Dayane Reis@, Michael T. Niemier and X. Sharon Hu, “FeFET-CiM: A Computing in Memory Solution to Reduce the Overheads Associated with Data Transfer,” at TECHCON, Austin, TX, 2018.
  22. Indranil Palit@, Lin Yang, Danny Chen, Michael Niemier, Jinjun Xiong, and X. Sharon Hu, “Biomedical Image Segmentation using Fully Convolutional Networks on True North,” IEEE International Symposium on Computer-Based Medical Systems, 2018.
  23. Dayane Reis@, Xunzhao Yin@, Michael Niemier, and X. Sharon Hu, “Computing in Memory with FeFETs,” International Symposium on Low Power Electronic Design (ISLPED), p. 24, July 2018.
  24. Xiaoming Chen+, Michael Niemier, Xiaobo Sharon Hu, “Non-volatile Lookup Table Design Based on Ferroelectric Field-Effect Transistors (FeFETs),” at International Symposium on Circuits and Systems (ISCAS), 2018.
  25. Xiaoming Chen+, Xunzhao Yin@, Michael Niemier, and Xiaobo Sharon Hu, “Design and Optimization of FeFET-based Crossbars for Binary Convolutional Neural Networks,” at Design, Automation, and Test in Europe (DATE), 2018.
  26. Ahmedullah Aziz, Evelyn T. Breyer, An Chen, Xiaoming Chen+, Suman Datta, Sumeet Kumar Gupta, Michael Hoffmann, Xiaobo Sharon Hu, Adrian Ionescu, Matthew Jerry@, Thomas Mikolajick, Halid Mulaosmanovic, Kai Ni+, Michael Niemier, Ian O'Connor, Atanu Saha, Stefan Slesazeck, Sandeep Krishna Thirumala, and Xunzhao Yin@, “Computing with Ferroelectric FETs: Devices, Models, Systems, and Applications,” at Design, Automation, and Test in Europe (DATE), 2018.
  27. R. Perricone@, M. Niemier, and X.S. Hu, “Challenges and Opportunities with Spin-based Logic”, at SPIE (Nanoscience & Engineering), Spintronics X, 10357, 103570M, 2017.
  28. Suman Datta, Alan Seabaugh, Michael Niemier, Arijit Raychowdhury, Darrell Schlom, Debdeep Jena, Grace Xing, H-S Philip Wong, Eric Pop, Sayeef Salahuddin, Sumeet Gupta, Supratik Guha, “In Quest of the Next Information Processing Substrate,” at Design Automation Conference (DAC), Article 17, 2017.
  29. Jian-Ping Wang, Sachin S Sapatnekar, Chris H Kim, Paul Crowell, Steve Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, X Sharon Hu, Michael Niemier, Azad Naeemi, Chia-Ling Chien, Caroline Ross, Roland Kawakami, “A Pathway to Enable Exponential Scaling for the Beyond CMOS Era,” at Design Automation Conference (DAC), Article 16, 2017.
  30. Robert Perricone@, Li Tang, M. Niemier, X.S. Hu, “Exploiting Non-Volatility for Information Processing,” at Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), p. 305-310, 2017.
  31. Xunzhao Yin@, Michael Niemier, X Sharon Hu, “Design and benchmarking of ferroelectric FET-based TCAM,” at Design Automation and Test in Europe (DATE), p. 1444-1449, 2017.
  32. Robert Perricone@, Ibrahim Ahmed, Zhaoxin Liang, Meghna G Mankalale, X Sharon Hu, Chris H Kim, Michael Niemier, Sachin S Sapatnekar, Jian-Ping Wang, “Advanced Spintronic Memory and Logic for Non-Volatile Processors,” at Design Automation and Test Europe (DATE), p. 972-977, 2017.
  33. András Horváth, Michael Hillmer*, Qiuwen Lou@, X. Sharon Hu, and Michael Niemier, “Cellular Neural Network Friendly Convolutional Neural Networks – CNNs with CNNs,” at Design Automation and Test Europe (DATE), p. 145-150, 2017.
  34. Xunzhao Yin@, Aziz Ahmedullah, Joseph Nahas, Sumeet Gupta, Suman Datta, Michael Niemier and X, Sharon Hu, “Exploiting Ferroelectric FETs for Low-Power Non-Volatile Logic-in-Memory Circuits,” at International Conference on Computer Aided Design (ICCAD), Article 121, November 7-10, 2016.
  35. Craig Lent, Kenneth Henderson, Enrique Blair, S. Alex Kandel, Steven Corcelli, Peter Kogge, Yuhui Lu, John Christie, Natlie Wasio, Rebecca Quardokus, Ryan Forrest, Ryan Brown, Michael Niemier, Gregory Snider, Alexei Orlov, Angela Silski, David Turner, Jacob Peterson, “Molecular Cellular Networks: A Non von Neumann Architecture for Molecular Electronics,” at IEEE Conference on Rebooting Computing, San Diego, October 17-19, 2016.
  36. Robert Perricone@, Michael Niemier, X. Sharon Hu, and Joseph Nahas, “Can Beyond CMOS Devices Illuminate Dark Silicon,” at SRC TECHCON, Austin, TX, September 11-13, 2016.
  37. Kevin Leyden@, Miklós Koller, Michael Niemier, James Schmiedeler, and György Cserey, “Kinect image processing by CNN algorithm for gait recognition,” at 15th International Workshop on Cellular Nanoscale Networks and their Applications, 2016.
  38. Nathan Spulak+, Sá́ndor Fö̈ldi,† Mikkós Koller, Michael Niemier, James Schmiedeler, and György Cserey, “Wrist pulse detection and analysis using three in-line sensors and linear actuators,” at 15th International Workshop on Cellular Nanoscale Networks and their Applications, 2016.
  39. Hannah Juarez+, James P. Schmiedeler, Michael Niemier, and Györegy Cserey, “Designing a Tactile Sensor Array for Shape Recognition,” at 15th International Workshop on Cellular Nanoscale Networks and their Applications, 2016.
  40. Yu Bi, X. Sharon Hu, Yier Jin, Michael Niemier, and Xunzhao Yin@, “Enhancing Hardware Security with Emerging Transistor Technologies,” at Great Lakes Symposium on VLSI, May 18-20, Boston, MA, p. 305-310, 2016.
  41. Xunzhao Yin@, Behnam Sedighi+, X. Sharon Hu, and Michael Niemier, “Design of Latches and Flip-Flops using Emerging Tunneling Devices,” at Design, Automation, and Test in Europe (DATE), p. 367-372, 2016.
  42. An Chen, X. Sharon Hu, Yier Jin, Michael Niemier, and Xunzhao Yin@, “Using Emerging Technologies for Hardware Security Beyond PUFs,” at Design, Automation, and Test in Europe (DATE), p. 1544-1549, 2016.
  43. Robert Perricone@, X. Sharon Hu, Joseph Nahas, and Michael Niemier, “Can Beyond-CMOS Devices Illuminate Dark Silicon,” at Design, Automation, and Test in Europe (DATE), p. 13-18, 2016.
  44. Indranil Palit@, Qiuwen Lou@, Nicholas Acampora, Joseph Nahas, Michael Niemier, and X. Sharon Hu, “Analytically Modeling Power and Performance of a CNN System,” at International Conference on Computer Aided Design (ICCAD), p. 186-193, 2015.
  45. Kaveh Shamsi, Yu Bi, Yier Jin, Pierre-Emmanuel Gaillardon, Michael Niemier and X. Sharon Hu, “Reliable and High Performance STT-MRAM Architectures based on Controllable-Polarity Devices,” at International Conference on Computer Design (ICCD), p. 343-350, 2015.
  46. Stephan Breitkreutz-v. Gamm, Irina Eichwald, Grazvydas Ziemys, György Csaba+, Gary Bernstein, Michael Niemier, Wolfgang Porod, Mariagrazia Graziano, Doris Schmitt-Landsiedel, and Markus Becherer, “Towards Nanomagnetic Logic systems: A Programmable Arithmetic Logic Unit for Systolic Array-based Computing”, at IEEE Nanotechnology Materials and Devices Conference (NMDC), 2015.
  47. Qiuwen Lou@, Indranil Palit@, Andras Horvath, X. Sharon Hu, Michael Niemier, and Joseph Nahas, “TFET-based Operational Transconductance Amplifier Design for CNN Systems,” at Great Lakes Symposium on VLSI (GLSVLSI), p. 320-325, 2015.
  48. Robert Perricone@, Yining Zhu, Katherine Sanders, X. Sharon Hu, and Michael Niemier, “Towards Systematic Design of 3D pNML Layouts,” at Design, Automation, and Test in Europe (DATE), p. 1539-1542, 2015.
  49. Behnam Sedighi+, Indranil Palit@, Xiaobo Sharon Hu, Joseph Nahas, and Michael Niemier, at “A CNN-inspired mixed signal processor based on tunnel transistors,” Design, Automation, and Test in Europe (DATE), p. 1150-1155, 2015.
  50. Y. Bi, P.-E. Gaillardon, X. Hu, M. Niemier, J.-S. Yuan, and Y. Jin, “Leveraging emerging technology for hardware security - case study on silicon nanowire FETs and graphene SymFETs,” at IEEE Asia Test Symposium (ATS), 2014, p. 342–347.
  51. Indranil Palit@, Qiuwen Lou@, Sharon Hu, Joseph Nahas, Michael Niemier, and Behnam Sedighi+, “Cellular Neural Networks for Image Analysis Using Steep Slope Devices,” at International Conference on Computer Aided Design (ICCAD), p. 92-95, 2014.
  52. Behnam Sedighi+, Xiaobo Sharon Hu, Joseph J. Nahas, and Michael Niemier, "Boolean Circuit Design using Emerging Tunneling Devices", at International Conference on Computer Design (ICCD), p. 355-360, 2014.
  53. Nandhini Chandramoorthy, Karthik Swaminathan, Matthew Cotter, Xueqing Li, Indranil Palit@, Kevin Irick, Sharon Hu, Michael Niemier, and Vijaykrishnan Narayanan, “Understanding the Landscape of Accelerators for Vision,” at IEEE International Workshop on Signal Processing Systems (SIPS), p. 1-6, 2014.
  54. A. Horváth, X.S. Hu, J. Nahas, M. Niemier, I. Palit@, R. Perricone@, and B. Sedighi+, “Architectural Impacts of Emerging Transistors,” at IEEE NEWCAS, p. 69-72, June 22-25, 2014.
  55. K. Haughan, M.T. Niemier, W. Porod, and G. Csaba+, “Cellular Automata designs for out-of-plane Nanomanget Logic,” at International Workshop on Computational Electronics (IWCE), p. 1-4, 2014.
  56. Indranil Palit@, Behnam Sedighi+, András Horváth, X. Sharon Hu, Joseph Nahas, and Michael Niemier, “Impact of Steep-Slope Transistors on Non-Von Neumann Architectures: CNN Case Study,” at Design Automation and Test Europe (DATE), 2014.
  57. Karthik Swaminathan, Moon Seok Kim, Nandhini Chandramoorthy, Behnam Sedighi+, Robert Perricone@, Jack Sampson and Vijaykrishnan Narayanan, “Modeling Steep Slope Devices: From Devices to Architecture,” Design Automation and Test Europe (DATE), 2014.
  58. Robert Perricone@, X. Sharon Hu, Joseph Nahas, and Michael Niemier, “Design of 3D Nanomagnet Logic Circuits: a Full-Adder Case Study,” at Design Automation and Test Europe (DATE), 2014.
  59. Stephan Breitkreutz, Irina Eichwald, Josef Kiermaier, Adam Papp@, György Csaba+, Michael Niemier, Wolfgang Porod, Doris Schmitt-Landiedel, and Markus Becherer, “1-Bit Full Adder in Perpendicular Logic using a Novel 5-input Majority Gate,” at EPJ Web of Conferences 75, 05001 (2014).
  60. Peng Li@, Faisal Shah@, Gyorgy Csaba+, Michael T. Niemier, Xiaobo S. Hu, Joseph J. Nahas, Wolfgang Porod, Gary H. Bernstein, “Application of "Snow Jet" Process in Fabrications of Nanomagnet Logic Devices,” at 58th Annual Magnetism and Magnetic Materials Conference, Denver, CO, November 4th-8th, 2013.
  61. Peng Li@, Faisal Shah@, Gyorgy Csaba+, Michael Niemier, X. Sharon Hu, Joseph Nahas, Wolfgang Porod, and Gary H. Bernstein, "Power Reduction in Nanomagnet Logic Using High-Permeability Dielectrics," at SRC TECHCON, Austin, TX, Sept. 9-10, 2013.
  62. Indranil Palit@, Xiaobo Sharon Hu, Joseph J. Nahas, and Michael T. Niemier, “TFET-based Cellular Neural Network Architectures,” at Proceedings of International Symposium on Low Power Electronics and Design, Beijing, China, September 4th-6th, 2013.
  63. S. Breitkreutz, I. Eichwald, J. Kiermaier, G. Csaba+, M. Niemier, W. Porod, D. Schmitt-Landsiedel, and M. Becherer, “1-Bit Full Adder in Perpendicular Nanomagnetic Logic Using a Novel 5-Input Majority Gate,” at Joint European Magnetic Symposium, 2013.
  64. Kevin Haughan, Michael Niemier, Wolfgang Porod, and György Csaba+, “Cellular Automata Designs for Out of Plane Nanomagnet Logic,” at 13th IEEE International Conference on Nanotechnology (IEEE-NANO), 2013.
  65. Li Tang, Xiaobo Sharon Hu, Danny Ziyi Chen, Michael T. Niemier, Richard F. Barrett, Simon D. Hammond and Ming-Yu Hsieh, “GPU Acceleration of Data Assembly in Finite Element Methods and Its Energy Implications,” at 24th IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 2013.
  66. S. Liu&, G. Csaba+, X.S. Hu, M.T. Niemier, W. Porod, and G. Bernstein, “Minimum-Energy State Guided Physical Design for Nanomagnet Logic,” at Design Automation Conference, 2013, Article 106; DOI: 10.1145/2463209.2488865.
  67. Peng Li@, Gyorgy Csaba+, Michael Niemier, Xiaobo Sharon Hu, Joe Nahas, Wolfgang Porod, and Gary Bernstein, “Vibrating Sample Magnetometry Study of High-Permeability Dielectrics on Nanomagnets,” at International Conference on Frontiers of Characterization and Metrology for Nanoelectronics, at NIST, Gaithersburg, MD, 2013.
  68. Indranil Palit@, Xiaobo Sharon Hu, Joseph Nahas, and Michael Niemier, “Systematic Design of Nanomagnet Logic Circuits,” at Design Automation and Test Europe, 2013, p. 1795-1800. (24.8% acceptance rate)
  69. Peng Li@, György Csaba+, Vijay K. Sankar+, X. Sharon Hu, Michael Niemier, Wolfgang Porod, Gary H. Bernstein, “Paths to Clock Power Reduction via High Permeability Dielectrics for Nanomagnet Logic Circuits,” at Joint MMM/Intermag Conference, Chicago, IL, 2013.
  70. Mohammad A Siddiq@, Gary H. Bernstein, Michael T. Niemier, Xiaobo S. Hu, Gyorgy Csaba+, Wolfgang Porod, “Demonstration of Field-Coupled Input Scheme on Line of Nanomagnets,” at Joint MMM/Intermag Conference, Chicago, IL, 2013.
  71. E. Varga@, M.T. Niemier, G. Csaba+, G.H. Bernstein, and W. Porod, “Experimental Realization of a Nanomagnet Full Adder Using Slanted-Edge Input Magnets,” at Joint MMM/Intermag Conference, Chicago, IL, 2013.
  72. Steve Kurtz@, Aaron Dingler@, Michael Niemier, Xiaobo Sharon Hu, György Csaba+, Joseph Nahas, Wolfgang Porod, and Gary Bernstein, “Preserving Steady State Non-Volatility in Nanomagnet Logic Circuits,” at SRC’s TECHCON: Technology and Talent for the 21st Century, September 10-11, 2012.
  73. Peng Li@, Gyorgy Csaba+, Vijay Karthik Sankar+, Xueming Ju, Edit Varga@, Paolo Lugli, Xiaobo Sharon Hu, Michael T. Niemier, Wolfgang Porod, Gary H. Bernstein, “Direct Measurement of Magnetic Coupling Between Nanomagnets for Nanomagnet Logic Applications,” at SRC’s TECHCON: Technology and Talent for the 21st Century, September 10-11, 2012.
  74. Mohammad Siddiq@, Gary H. Bernstein, Michael T. Niemier, Wolfgang Porod, Xiaobo Sharon Hu, “Experimental Demonstration of Field-Coupled Input Scheme for Nanomagnet Logic (NML),” at SRC’s TECHCON: Technology and Talent for the 21st Century, September 10-11, 2012.
  75. M. Niemier, X. Ju, M. Becherer, G. Csaba+, A Dingler@, X.S. Hu, D. Schmitt-Landsiedel, P. Lugli, and W. Porod, “Boolean and Non-Boolean Architectures for Out-of-Plane Nanomagnet Logic,” at International Workshop on Cellular Nanoscale Networks and their Applications, August 29-31, p. 1-6, 2012.
  76. Wolfgang Porod, Peng Li@, Faisal Shah@, Mohammad Siddiq@, Edit Varga@, Gyorgy Csaba+, Vijay Sankar+, Gary H. Bernstein, X. Sharon Hu, Michael Niemier, Joseph Nahas, and Alexei Orlov, “NanoMagnet Logic,” at Device Research Conference, p. 213-14, June 18-20, 2012.
  77. Peng Li@, Gyorgy Csaba+, Vijay K. Sankar+, X. Sharon Hu, Michael Niemier, Wolfgang Porod, and Gary H. Bernstein, “Power Reduction in Nanomagnet Logic Clocking through High Permeability Dielectrics,” at Device Research Conference, p. 129-130, June 18-20, 2012.
  78. M. Niemier, X. Ju, M. Becherer, G. Csaba+, X.S. Hu, D. Schmitt-Landsiedel, P. Lugli, and W. Porod, “Systolic Architectures and Applications for Nanomagnet Logic,” at Silicon Nanoelectronics Workshop, June 10-11, 2012.
  79. Xueming Ju, Markus Becherer, Paolo Lugli, Michael T. Niemier, Wolfgang Porod, and György Csaba+, “Design of a Systolic Pattern Matcher for Nanomagnet Logic,” at International Workshop on Computational Electronics, p. 1-3, May 22-25, 2012.
  80. Aaron Dingler@, Steve Kurtz@, Michael Niemier, X Sharon Hu, Gyorgy Csaba+, Joesph Nahas, Wolfgang Porod, Gary Bernstein, Peng Li@, Vijay Karthik Sankar+, “Making Non-Volatile Nanomagnet Logic Non-Volatile,” at Design Automation Conference (DAC), p. 476-485, 2012. (22% acceptance rate)
  81. Peng Li@, Gyorgy Csaba+, Vijay K. Sankar+, Xueming Ju, X. Sharon Hu, Michael Niemier, Wolfgang Porod, Gary H. Bernstein, “Direct Measurement of Magnetic Coupling between Nanomagnets for NML Applications,” in Proceedings of INTERMAG, May 7-11, 2012. (Best student paper nominee, oral presentation).
  82. Peng Li@, Vijay K. Sankar+, Gyorgy Csaba+, Faisal Shah@, X. Sharon Hu, Michael Niemier, Wolfgang Porod, Gary H. Bernstein, “Enhanced Permeability Dielectrics for Power Reduction in NML Circuits,” in Proceedings of Intermag, May 7-11, 2012 (oral presentation).
  83. Peng Li@, Gyorgy Csaba+, Vijay K. Sankar+, X. Sharon Hu, Michael Niemier, Wolfang Porod, Gary H. Bernstein, “Switching Behavior of Lithographically Fabricated Nanomagnets for Logic Applications,” at Magnetism and Magnetic Materials (MMM), October, 2011, Scottsdale, AZ.
  84. Shiliang Liu&, X. Sharon Hu, Joseph J. Nahas, Michael Niemier, Gary H. Bernstein, and Wolfgang Porod, “Magnetic-Electrical Interface for Nanomagnet Logic” at SRC’s TECHCON: Technology and Talent for the 21st Century'', 2011.
  85. Shiliang (Shawn) Liu&, Xiaobo S. Hu, Joseph J. Nahas, Michael T. Niemier, at Work in Progress session at the 2011 Design Automation Conference (DAC).
  86. György Csaba+, Paolo Lugli, Michael Niemier and Wolfgang Porod, “Magnetic excitations for information processing,” at 12th IEEE CNNA - International Workshop on Cellular Nanoscale Networks and Applications, p. 1-5, February 3-5, 2010.
  87. Steve Kurtz@, Michael Niemier, X. Sharon Hu, Wolfgang Porod, and Gary H. Bernstein, “Design Space Exploration for Nanomagnet Logic Systems”, in Proceedings of Foundations of Nanoscience (FNANO 10) (Snowbird, UT), p. 62-63, April 27-30, 2010 (invited).
  88. M. Alam@, G.H. Bernstein, J. Bokor, D. Carlton, X.S. Hu, S. Kurtz@, B. Lambson, M.T. Niemier, W. Porod, M. Siddiq@, and E. Varga@, “Experimental Progress of and Prospects for Nanomagnet Logic (NML),” at Silicon Nanoelectronics Workshop (Hawaii), p. 1-2, June 15-17, 2010.
  89. Michael Crocker&, X. Sharon Hu, and Michael Niemier, “Design and Comparison of NML Systolic Architectures”, at IEEE/ACM International Symposium on Nanoscale Architectures (Anaheim, CA), p. 29-34, June 17-18, 2010. (33% acceptance rate)
  90. E. Varga@, S. Liu&, M.T. Niemier, W. Porod, X.S. Hu, G.H. Bernstein, and A. Orlov, “Experimental Demonstration of Fanout for Nanomagnet Logic,” at Device Research Conference, p. 95-96, 2010.
  91. Edit Varga@, Michael T. Niemier, Gary H. Bernstein, Wolfgang Porod, and X. Sharon Hu, “Programmable Nanomagnet-Logic Majority Gate,” at Device Research Conference, p. 85-86, 2010.
  92. E. Varga@, M. Siddiq@, M.T. Niemier, M.T. Alam@, G.H. Bernstein, W. Porod, X.S. Hu, and A. Orlov, “Experimental Demonstration of Non-Majority, Nanomagnet Logic Gates,” at Device Research Conference, p. 87-88, 2010.
  93. E. Varga@, M. Siddiq@, M. Niemier, G.H. Bernstein, and W. Porod, “Experimental Investigation of Slanted Supermalloy Nanomagnets and Their Application in Nanomagnet Logic”, at SRC’s TECHCON: Technology and Talent for the 21st Century'', 2010.
  94. G. H. Bernstein, J. Kulick, D. Kopp, J. Bonath, J. Brockman, W. Buckhanan, S. Dai, P. Fay, M. Khan, A. Kriman, Y. Lee, C. Liang, M. Niemier, M. Padberg, D. Rinzler, R. Savino, and G. Snider, “Quilt Packaging – a Quasi-Monolithic Way to Merge Heterogeneous Technologies and Scales,” in Proceedings of Foundations of Nanoscience (FNANO09) (invited, keynote).
  95. M. T. Alam@, S. Kurtz@, M.T. Niemier, S. X. Hu, G. H. Bernstein, and W. Porod, “Magnetic Logic Based on Field-Coupled Nanomagnets: Clocking Structures and Power Analysis,” in Proceedings of Foundations of Nanoscience (FNANO09) (invited).
  96. E. Varga@, M. T. Niemier, G.H. Bernstein, W. Porod, and X. Sharon Hu, “Non-volatile and Reprogrammable MQCA-based Majority Gates,” at Device Research Conference, p.1-2, June 22, 2009.
  97. A. Dingler@, M.T. Niemier, X.S. Hu, M.T. Alam@, and M. Garrison, “System-Level Energy and Performance Projections for Nanomagnet-based Logic,” in at IEEE Symposium on Nanoscale Architectures, p.21-26, July 30-31, 2009 (best paper award).
  98. M.T. Alam@, M.A. Siddiq@, M.T. Niemier, X.S. Hu, W. Porod, and G. H. Bernstein, “Fabrication of On-Chip Clock Structure for Nanomagnet QCA (MQCA),” at SRC’s TECHCON: Technology and Talent for the 21st Century'' (best student presentation award), 2009.
  99. A. Dingler@, M.J. Siddiq@, M.T. Niemier, X.S. Hu, M.T. Alam@, G.H. Bernstein, and W. Porod, “Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power,” at IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, p.94-102, October 7-9, 2009.
  100. M. Crocker&, X. Sharon Hu, and M. Niemier, “Defect Tolerance in QCA-Based PLAs,” at IEEE/ACM International Symposium on Nanoscale Architectures, p.46-53, Anaheim, CA, June 12-13, 2008. (27% acceptance rate)
  101. M. T. Alam@, S. Kurtz@, M.T. Niemier, S. X. Hu, G. H. Bernstein, and W. Porod, “Magnetic Logic Based on Field-Coupled Nanomagnets: Clocking Structures and Power Analysis,” in at 8th IEEE International Conference on Nanotechnology, Arlington, TX, p. 637, August 18-21, 2008 (invited paper).
  102. M. Niemier, A. Dingler@, and X. Sharon Hu, “Design Tradeoffs for Improved Performance in MQCA-based Systems,” at 1st IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems (NDCS), Cambridge, MA, Sept. 29-30, p. 35-38, 2008.
  103. M. Niemier, M. Crocker&, and X. Sharon Hu, “Fabrication Variations and Defect Tolerance for Nanomagnet-based QCA,” at 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cambridge, MA, Oct. 1-3, p. 534-542, 2008.
  104. M. Niemier, A. Dingler@, X. Sharon Hu, M. Tanvir Alam@, G. Bernstein, and W. Porod, “Bridging the Gap between Nanomagnetic Devices and Circuits,” at 26th IEEE International Conference on Computer Design, Lake Tahoe, CA, Oct. 12-15, p. 506-513, 2008 (34% acceptance rate).
  105. X.S. Hu and M.T. Niemier, “Computing with nearest neighbor interactions: a nanomagnetic implementation,” at 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, Atlanta, GA, Oct. 19-24, 2008, p. 223-330 (invited paper).
  106. M. T. Alam@, G. H. Bernstein, W. Porod, S. Hu, M. Niemier, M. Putney@, and J. DeAngelis@, “Power Dissipation for Clocked Magnetic QCA,” at 12th International Workshop on Computational Electronics, October 8-10, 2007, Amherst, MA.
  107. M. Niemier, M.T. Alam@, X.S. Hu, G. Bernstein, W. Porod, M. Putney@, and J. DeAngelis@, “Clocking Structures and Power Analysis for Nanomagnet-based Logic Devices,” at International Symposium on Low Power Electronics and Design (ISLPED), p. 26-31, 2007. (29% acceptance rate)
  108. M. Crocker&, X.S. Hu, and M.T. Niemier, “Fault Models and Yield Analysis for QCA-based PLAs,” at 17th International Conference on Field Programmable Logic and Applications (FPL), p. 435-440, Amsterdam, Netherlands, August 27-29, 2007.
  109. A. Chaudhary, D.Z. Chen, R. Fleischer, X.S. Hu, J. Li, M.T. Niemier, Z. Xie, and H. Zhu, “Approximating the Maximum Sharing Problem,” at Workshop on Algorithms and Data Structures, Halifax, Canada, p. 52-63, August 15-17, 2007.
  110. G. Bernstein, M. Alam@, W. Porod, S. Hu, M. Niemier, M. Putney@, and J. DeAngelis@, “Clocking Scheme for Nanomagnet QCA (NMQCA),” at 7th IEEE International Conference on Nanotechnology, Hong Kong, p. 403-408, August 2-5, 2007.
  111. M.T. Alam@, M. Niemier, W. Porod, S. Hu, M. Putney@, J. DeAngelis@, and G. Bernstein, “On-Chip Clocking Scheme for Nanomagnet QCA,” at Device Research Conference, p.133-134, Notre Dame, IN, June 18-20, 2007.
  112. M.T. Niemier, X.S. Hu, M. Lieberman, and M. Crocker&, “Using CAD to Shape Experiments in QCA,” at International Conference on Computer Aided Design (ICCAD), p. 907-914, November 8, 2006 (25.1% acceptance rate).
  113. M.T. Niemier, X.S. Hu, M. Lieberman, M. Crocker&, Pavan Sadarangani, Zack Capozzi, and Tim Dysart, “Using DNA as a Circuitboard for a Molecular QCA PLA,” in the Proceedings of Foundations of Nanoscience (FNANO06), p. 96-107, April 23 - April 27th, 2006 (invited paper).
  114. X.S. Hu, M. Crocker&, M.T. Niemier, M.Yan, and G. Bernstein, “PLAs in Quantum-dot Cellular Automata,” at International Symposium on VLSI, p. 242-247, March 2-3, 2006.
  115. A. Chaudhary, D.Z. Chen, X.S. Hu, M.T. Niemier, R. Ravichandran@, K. Whitton, “Eliminating Wire Crossings for Molecular Quantum-dot Cellular Automata Implementation,” at Proceedings of the International Conference on Computer Aided Design (ICCAD), Nov. 6-10, p. 565-571, 2005 (25% acceptance rate).
  116. R. Ravichandran@, M.T. Niemier, and S.K. Lim, “Partitioning and Placement for Buildable QCA Circuits,” at IEEE/ACM Asia South Pacific Design Automation Conference, p. 424-427, 2005.
  117. M.T. Niemier, R. Ravichandran@, and P.M. Kogge, “Using Circuits and Systems Research to Drive Nanotechnology,” at International Conference on Circuit Design, p. 302-309, October 11-13, 2004 (invited paper).
  118. D.A. Antonelli, T.J. Dysart, D.Z. Chen, A.B. Kahng, P.M. Kogge, R.C. Murphy, and M.T. Niemier, “Quantum-Dot Cellular Automata (QCA) Circuit Partitioning: Problem Modeling and Solutions,” at 41st Design Automation Conference, p. 363-368, June 7-11, 2004, San Diego, CA. (21% acceptance rate).
  119. R. Ravichandran@, N. Ladiwala, J. Nguyen, M.T. Niemier, S.K. Lim, “Automatic Cell Placement for Quantum-dot Cellular Automata,” at 14th Great Lakes Symposium on VLSI, Boston, MA, April 2004, p. 332-337.
  120. M.T. Niemier and P.M. Kogge, “The 4-Diamond Circuit - A Minimally Complex Nano-scale Computational Building Block in QCA,” at IEEE Computer Society Symposium on VLSI, p. 3-10, IEEE Computer Society Press, Lafayette, LA, February 2004.
  121. M.T. Niemier and P.M. Kogge, “Teaching Students Computer Architecture for New Nanotechnologies,'' in Proceedings of the Workshop on Computer Architecture Education (WCAE), held in conjunction with the 29th International Symposium of Computer Architecture (ISCA), Anchorage, AK, May 2002.
  122. M.T. Niemier, A.F. Rodrigues, and P.M. Kogge, “A Potentially Implementable FPGA for Quantum Dot Cellular Automata,” in Proceedings of the 1st Workshop on Non-Silicon Computation (NSC-1), held in conjunction with the 8th International Symposium on High Performance Computer Architecture (HPCA-8), Boston, MA, p. 38-45, February 2002.
  123. M.T. Niemier and P.M. Kogge, “Exploring and Exploiting Wire-Level Pipelining in Emerging Technologies,” at 28th International Symposium of Computer Architecture, p. 166-177, IEEE Computer Society Press, Goteburg, Sweden, July 2001.
  124. M.T. Niemier, M.J. Kontz, and P.M. Kogge, “A Design of and Design Tools for a Novel Quantum Dot Based Microprocessor,” at 37th Design Automation Conference, p. 227-232, Association for Computer Machinery (ACM) Press, Los Angeles, CA, June 2000.
  125. M.T. Niemier and P.M. Kogge, “Logic in Wire: Using Quantum Dots to Implement a Microprocessor,” at International Conference of Electronics, Circuits, and Systems, p.1211-1215, Vol. 3 IEEE Computer Society Press, Larnaca, Cyprus, September 1999.
  126. M.T. Niemier and P.M. Kogge, “Designing Complex Logic Systems with QCA Devices,” at 9th Great Lakes Symposium on VLSI, p. 122-125, IEEE Computer Society Press, Ann Arbor, MI, March 2-4, 1999.
  127. M.T. Niemier and P.M. Kogge, “Logic-in-Wire: Using Quantum Dots to Implement Really Dense Processing Logic,” at Third Petaflops Workshop held in conjunction with Frontiers of Massively Parallel Processing, Annapolis, MD, February 1999.

Invited Book Chapters

  1. Wolfgang Porod, Gary H Bernstein, György Csaba+, Sharon X Hu, Joseph Nahas, Michael T. Niemier, Alexei Orlov, “Nanomagnet Logic (NML),” in Field Coupled Nanocomputing, Springer Berlin Heidelberg, p. 21-32, 2014.
  2. Michael T. Niemier, György Csaba+, Wolfgang Porod, “Nanomagnet Logic (NML): A Magnetic Implementation of Quantum-dot Cellular Automata,” in Emerging Nanoelectronic Devices.
  3. György Csaba+, Gary H. Bernstein, Alexi Orlov, Michael T. Niemier, X. Sharon Hu, and Wolfgang Porod, “From magnetic ordering to magnetic computing,” Chapter 12 in CMOS and Beyond, Kelin Kuhn, editor, ISBN-13: 978-1107043183, p. 301-331.
  4. M.T. Niemier and W. Porod, “Nanomagnet Logic,” CRC Handbook on Nanotechnology, 2011.
  5. M.T. Niemier and P.M. Kogge, “Origins of Design Rules for QCA,” in Nano, Quantum, and Molecular Computation, Iris Bahar and Sandeep Shukla (Editors), p. 267-292, Kluwer Press, June 2004.
  6. J. Nguyen, R. Ravichandran@, S.K. Lim, and M.T. Niemier, “Origins of CAD tools for QCA Systems,” in Nano, Quantum, and Molecular Computation, Iris Bahar and Sandeep Shukla (Editors), p. 295-316, Kluwer Press, June 2004.
  7. C.S. Lent, G.L. Snider, G. Bernstein, W. Porod, A. Orlov, M. Lieberman, T. Fehlner, M.T. Niemier, and P.M. Kogge, “Quantum-Dot Cellular Automata,” chapter in Electron Transport in Quantum Dots, p. 397-433, Johahtan P. Bird (ed.), Kluwer Academic Publishers, 2003.

Patents

  1. Systems and methods for filtering and computation using tunneling transistors, B Sedighi+, XS Hu, M Niemier, J Nahas, US Patent 9,825,132 – granted 2017.
  2. Mixed signal processors, B Sedighi+, M Niemier, XS Hu, I Palit@, US Patent 9,712,146 – granted 2017.
  3. Pixel cell having a reset device with asymmetric conduction, Jorge Fernandez-Berni, Michael Niemier, Xiabobo Sharon Hu, Ricardo Carmona-Galan, Angel Rodriguez-Vazquez, US Patent Application. 15/220,473
  4. SymFET-based Boolean Gates for Digital Processing, Xiaobo Sharon Hu, Joseph J. Nahas, Michael T. Niemier, and Behnam Sedighi+. (Issued June 7, 2016 – 9,362,919 – “SymFET-based Boolean Gates”)
  5. G. H. Bernstein, S. Hu, M. Niemier, W. Porod, M. T. Alam@, and E. Varga@, “Non-Majority MQCA Magnetic Logic Gates and Arrays Based on Misaligned Magnetic Islands,” UND-10-029; P1231 - L&P Ref: CU-8431. Issued 11/15/11 – 8,058,906.

Current Post-Doctoral Researchers

In Computer Science and Engineering:

  1. Ramin Rajaei + (advised by Niemier)

Current Graduate Research Assistants

In Computer Science and Engineering:

  1. Arman Kazemi @ (co-advised with X. Hu)
  2. Ann Franchesca Laguna@ (co-advised with X. Hu)
  3. Liu Liu @ (co-advised with X. Hu)
  4. Dayane Reis@ (co-advised with X. Hu)
  5. Mehdi Sharifi@ (co-advised with X. Hu)

Past Post-Doctoral Researchers

In Computer Science and Engineering:

  1. Indranil Palit + (co-advised with X. Hu)
  2. Xiaoming Chen + (co-advised with X. Hu)
  3. Benham Sedighi + (co-advised with X. Hu)
  4. György Csaba + (advised by Niemier)

Past Graduate Research Assistants

  1. Qiuwen Lou@, Ph.D., 2020, Amazon (co-advised with X. Hu)
  2. Xunzhao Yin@, Ph.D. 2019 Assistant Professor, Zhejiang University (co-advised with X. Hu)
  3. Robert Perricone@, Ph.D. 2018, IBM (co-advised with X. Hu)
  4. Indranil Palit, Ph.D. 2016, post-doc on TrueNorth project, now at Valeo (co-advised with X. Hu)
  5. Aaron Dingler@, Ph.D. 2013, Seattle Pacific University (served as department chair); now at IBM (advised by Niemier)
  6. Steven Kurtz, Ph.D. 2013, IBM (advised by Niemier)
  7. M. Jafar Siddiq, Ph.D. 2013, Intel (co-advised with G. Bernstein; Ph.D. in Electrical Engineering)
  8. Wayne Buckhanan, Ph.D. 2013, Associate Professor, Andrews University (co-advised with G. Bernstein; Ph.D. in Electrical Engineering)
  9. M. Tanvir Alam, Ph.D. 2010, post-doctoral researcher at UC-Berkeley, now at Intel (co-advised with G. Bernstein; Ph.D. in Electrical Engineering)
  10. Michael Putney
    • (left program for Air Force, did not receive degree)
  11. Jarrett DeAngelis
    • (M.S. in Computer Engineering)